Memory devices have one or more arrays of memory cells for storing information. A bit of information is written to or read from a particular memory cell by selecting the row and column at the intersection of which is located the desired memory cell. Information is stored in the selected memory cell by either charging or discharging a capacitor associated with the cell. In some memory devices, charge stored on a memory cell capacitor leaks out over time. If memory cell leakage is not addressed, information stored in a memory device will be lost. To prevent data loss, information stored in memory devices is periodically refreshed. Examples of memory devices that may suffer from leakage include Dynamic Random Access Memory (DRAM) devices.
Data stored in a DRAM device is conventionally refreshed one row at a time. A row of memory cells is refreshed by selecting the row, reading the contents of the memory cells forming the row, and writing the same data back to the row. The predominant DRAM refresh operations are distributed and burst. During distributed refresh, memory access operations are evenly interspersed between refresh cycles. This way, data may be read from or written to a DRAM device between row refresh operations. During burst refresh, all refresh cycles are executed one right after the other until all rows have been refreshed. Thus, a DRAM device may not be accessed during a burst refresh. All addressable rows are typically refreshed during periodic distributed or burst refresh operations regardless of whether all rows are used when the DRAM device is active. However, some conventional approaches actively track which rows are accessed during normal DRAM operation, refreshing only the rows accessed during use. The circuit overhead needed to actively track which rows are accessed during normal operation becomes increasingly complex as the size of DRAM devices increase, thus consuming more chip area and power.